Field of the Invention
The present invention relates to a semiconductor integrated circuit, including a dynamic random access memory (generally abbreviated "DRAM") and having an ability to stably produce an intended output voltage.
Normally, in a semiconductor integrated circuit including a DRAM, a plurality of word lines and a plurality of pairs of bit lines crossing the word lines are arranged in the form of a matrix. A plurality of memory cells are formed at intersections between the word lines and bit lines. The memory cells constitute a memory cell array.
Assume that data of "1" or "0" is read from a memory cell selected from among the plurality of memory cells. The potential at a pair of bit lines to which the memory cell is connected is varied according to electric charges accumulated in a cell capacitor in the memory cell. The variation in the potential at the bit lines is detected by a sense amplifier. The variation in the potential at the bit lines must be detected reliably by using a current that is as small as possible (i.e., with minimum power consumption). A method normally adopted for this purpose will be described below. That is to say, before the electric charges which have been accumulated in the cell capacitor in the memory cell are redistributed on the pair of bit lines according to the capacitance offered by the bit lines, the bit lines are short-circuited. The bit lines are then precharged so that the potential at the bit lines will be equal to a certain supply voltage (for example, a half of a high-level supply voltage Vcc (=Vcc/2)).
On the other hand, a high-level supply voltage Vcc or a low-level supply voltage Vss (=0 V) is applied to a cell storage node of the capacitor in the memory cell. At this time, either the high-level supply voltage or the low-level supply voltage is applied depending on whether or not the memory cell has been selected. In a typical DRAM, the capacitance of a cell capacitor is required to be as large as possible in order to make the data holding time relatively long. For this purpose, it is necessary to reduce the thickness of an insulating film of the cell capacitor as much as possible. As the thickness of the insulating film decreases, the durability of the insulation of the cell capacitor, when a high voltage is applied to the cell capacitor, deteriorates. The potential at an electrode (cell plate node) opposed to the cell storage node of the cell capacitor is therefore set to Vcc/2. Thus, even when the supply voltage Vcc or Vss is applied to the cell storage node of the cell capacitor, a potential difference between both surfaces of the insulating film of the cell capacitor is merely Vcc/2. More specifically, in the case in which the potential at the electrode opposed to the cell storage node of the cell capacitor is set to Vcc/2, a voltage applied to the insulating film is only a half of a voltage applied thereto when the potential at the electrode opposed to the cell storage node of the cell capacitor is set to Vcc or Vss. Consequently, the capacitance of the cell capacitor can be made relatively large by reducing the thickness of the insulating film. This is advantageous in elongating the data holding time.
In recent years, especially, a DRAM has been required to operate with a supply voltage that is as low as possible, for example, a supply voltage (Vcc) which is equal to or less than 2 V. This is intended to minimize power consumption of the whole semiconductor integrated circuit. As mentioned above, in a typical DRAM, a voltage used to precharge the bit lines or the potential at an electrode opposed to a cell storage node of a cell capacitor is usually set to Vcc/2. Therefore, it is necessary to stably generate a relatively low voltage which is equal to or less than 1 V.
Now, referring to FIGS. 1 to 5 that will be mentioned later in "BRIEF DESCRIPTION OF THE DRAWINGS," an exemplary configuration of a bit line precharging circuit in a typical DRAM, and an exemplary structure of a memory cell, will be described below. A variation in the potential at bit lines occurring when the bit lines are precharged, and an exemplary configuration of a semiconductor integrated circuit having a conventional constant voltage generating circuit will also be described. The above description is intended to reveal the reasons why it is necessary to generate a voltage that is a half of a supply voltage Vcc (that is, Vcc/2) in the DRAM. Also, the above description is intended to clarify problems underlying the generation of the voltage Vcc/2 that is equal to or less than 1 V.
In FIG. 1, an outline configuration of a typical DRAM is shown.
As shown in FIG. 1, the typical DRAM has a memory cell array 100 in which a plurality of word lines and a plurality of pairs of bit lines are arranged in the form of a matrix. Moreover, a plurality of memory cells is formed at intersections between the word lines and bit lines. Furthermore, the DRAM includes a decoder 600 for decoding control address bits A0 to Am (where m is any positive integer equal to or larger than 1) that are inputted via an input buffer 500. The decoder 600 then produces a memory cell selection signal which is used to select a specific memory cell. The decoder 600 applies a certain boosted voltage Vpp (a voltage higher than a supply voltage Vcc that is an internal voltage) to a word line to which the specific memory cell is connected, and thus selects the word line. Output data is sensed or data is rewritten, whereby data is read from the specific memory cell or written into the specific memory cell.
Furthermore, the DRAM includes a sense amplifier 200. For reading a specific memory cell selected by the decoder 600, the sense amplifier 200 detects electric charges transferred from the cell capacitor Cc (See FIG. 3 that will be described later) in the specific memory cell. The sense amplifier 200 thus reads data from the memory cell. The data which has been read by the sense amplifier 200 is amplified up to a given level by a main amplifier 300. The resultant data is then outputted as digital I/O data of bits DQ0 to DQn (n=0, 1, 2, --) to the outside of the DRAM.
In the above-mentioned DRAM, it is the bit line pre-charging circuit and cell capacitor that require the voltage Vcc/2 that is half of the supply voltage Vcc (output voltage Vpr in FIGS. 2 and 3). Herein, the bit line precharging circuit is included in the sense amplifier 200 shown in FIG. 2. The cell capacitor is included in any memory cell 100 shown in FIG. 3. In FIG. 1, the sense amplifier 200 and memory cell 100 are hatched in an effort to explicitly show the components that use the voltage equivalent to half of the supply voltage Vcc.
To be more specific, the bit line precharging circuit in the sense amplifier 200 shown in FIG. 1 includes bit line precharging transistors 210, 220 and 230 which precharge a pair of bit lines BL and /BL to select the specific memory cell. One of the memory cell selection transistors (230) is realized by an NMOS transistor (n-channel MOS transistor) and has a source and a drain (or a drain and a source) thereof connected to the pair of bit lines BL and /BL, respectively, so as to equalize potentials at both of the pair of bit lines BL and /BL memory cell, and inputs a precharge enabling signal .phi. through a gate thereof. The other two bit line precharging transistors (210 and 220) are realized by two NMOS transistors for precharging the pair of bit lines BL and /BL. In this configuration, a drain (or source) of the bit line precharging transistor 210 is connected on one bit line BL. A drain (or source) of the other bit line precharging transistor 220 is connected to the other bit line /BL. Further, the sources (or drains) of the bit line precharging transistors 210 and 220 are connected to a common node. A precharging output voltage Vpr (for example, a half of a supply voltage Vcc (Vcc/2)) is applied to the common node. The precharge enabling signal .phi. is applied to each of the gates of the three bit line precharging transistors 210, 220 and 230.
Furthermore, any memory cell of a one-transistor and one-capacitor type, as shown in FIG. 3, is composed of one cell transistor Tc which is realized by an NMOS transistor and one cell capacitor Cc. For writing data "1" or "0" in this type of memory cell over the bit lines BL and /BL, a boosted voltage is applied to a gate of the cell transistor Tc over a word line WL. The cell transistor Tc is thus driven so as to enter an operating state (ON state). In this case, electric charges are accumulated in the cell capacitor Cc according to the data "1" or "0." Moreover, assuming that the memory cell is selected to read data from the memory cell, electric charges which have been accumulated in the cell capacitor Cc is redistributed on the pair of bit lines to which the memory cell is connected, according to a capacitance offered by the bit lines. The potential at the pair of bit lines is thus varied. The variation in potential at the bit lines is detected by the sense amplifier.
In FIG. 4, a timing chart indicating the variation in the potential at the bit lines occurring when the bit lines are precharged with half of the voltage Vcc, is shown. In FIG. 5, a timing chart indicating the variation in potential at the bit lines occurring when the bit lines are precharged with the supply voltage Vss (=0 V), is shown.
Based on the timing charts of FIGS. 4 and 5, the relationship between a voltage required to precharge bit lines and power consumption required to read data will be discussed below. Herein, assume that data "1" or "0" is read from a specific memory cell selected from among a plurality of memory cells. The variation in the potential at the pair of bit lines occurring when the bit lines are precharged with a voltage Vcc/2 is compared with the variation in the potential occurring when the bit lines are precharged with a voltage Vss (=0 V).
As shown in FIG. 4, before data is read from the specific memory cell which has become an active state, the pair of bit lines are precharged with the voltage Vcc/2. Assuming that the capacitance offered by the bit lines is Cb1, the amount of electric charges supplied from a high-voltage power supply for providing a supply voltage Vcc becomes (Vcc/2).multidot.Cb1 at the timing 1. The amount of electric charge becomes zero (0) at the time timing 2. This is because when the pair of bit lines BL and /BL offering the same capacitance is short-circuited and precharged, the potential at the bit lines automatically becomes equal to Vcc/2. According to the above technique for precharging the bit lines with the voltage Vcc/2, the amount of electric charges consumed for every cycle is (Vcc/2).multidot.Cb1. The amount of these electric charges is proportional to a current consumed for every cycle, that is, corresponding power consumption.
Assuming, as shown in FIG. 5, that before data is read from the specific memory remaining in the active state, the pair of bit lines is precharged with the voltage Vss (voltage provided by the low-voltage power supply (=0 V)). In this case, the amount of electric charges supplied from the high-voltage power supply that provides the supply voltage Vcc becomes Vcc.multidot.Cb1 at the timing 1. The amount of electric charges becomes 0 at the time instant 2. According to the above technique for precharging the bit lines with the voltage Vss, the amount of electric charges consumed for every cycle is Vcc.multidot.Cb1. The amount of these electric charges is also proportional to a current consumed for every cycle, that is, corresponding power consumption. The amount of electric charges consumed for every cycle according to the technique for precharging the bit lines with the voltage Vss is twice as large as that consumed according to the technique for pre-charging the bit lines with the voltage Vcc/2. In view of the above, the technique for precharging the bit lines with the voltage Vcc/2 is thought to be effective for reading data with power consumption which is as small as possible.
Further, in the memory cell shown in FIG. 3, the reasons why it is helpful to set the voltage at an electrode (cell plate node Nc) to the voltage Vcc/2 (=Vpr) will be described below. Herein, the above electrode is opposed to a cell storage node of the cell capacitor Cc.
Depending on whether or not the cell transistor Tc in the memory cell is in an operating state (ON state) or a non-operating state (OFF state), a voltage of "H (high)" level (high-level supply voltage Vcc) or a voltage of "L (low)" level (low-level supply voltage Vss) is applied to the cell storage node of the cell capacitor Cc shown in FIG. 3. For example, assume that the supply voltage Vss (=0 V) is applied to the cell plate node Nc of the cell capacitor Cc. When the voltage of "H" level is applied to the cell storage node of the cell capacitor Cc, a voltage difference equivalent to the supply voltage Vcc is applied between both surfaces of the insulating film of the cell capacitor. By contrast, assume that the supply voltage Vcc is applied to the cell plate node Nc of the cell capacitor Cc. When the voltage of "L" level is applied to the cell storage node of the cell capacitor Cc, a voltage difference equivalent to the supply voltage Vcc is also applied between both surfaces of the insulating film of the cell capacitor.
In contrast, assuming that the voltage Vcc/2 is applied to the cell plate node Nc of the cell capacitor Cc when either of the voltage of "H" level and the voltage of "L" level is applied to the cell storage node of the cell capacitor Cc, only a voltage difference equivalent to the voltage Vcc/2 is applied between both surfaces of the insulating film of the cell capacitor.
In the case of a typical DRAM, the capacitance of a cell capacitor is required to be as large as possible for attaining a high density of memory cells constituting a memory cell array. For this purpose, it is necessary to make the thickness of the insulating film of the cell capacitor as thin as possible. The thinner the insulating film is, the lower is a durability concerning an insulation of the cell capacitor when a high voltage is applied to the cell capacitor. By the way, assume that the voltage Vcc/2 is always applied to the cell plate node Nc of the cell capacitor. In this case, when either of a voltage of "H" level and a voltage of "L" level is applied to the cell storage node of the cell capacitor, only a voltage difference Vcc/2 is applied between both surfaces of the insulating film of the cell capacitor. In other words, assume that the voltage Vpr at the cell plate node Nc of the cell capacitor is set to Vcc/2. The voltage difference applied to the insulating film of the cell capacitor at this time is a half of the voltage difference applied when the voltage at the cell plate node Nc is set to the supply voltage Vcc or Vss. In this case, the voltage which is to be applied to an electrode opposed to the cell storage node of the cell capacitor Cc is a voltage Vcc/2. Consequently, the capacitance of the cell capacitor can be made relatively large by reducing the thickness of the insulating film.
In FIG. 6, a circuit diagram showing an exemplary configuration of a semiconductor integrated circuit including a conventional constant voltage generating circuit which has been devised in an effort to produce the voltage Vcc/2 stably, is illustrated.
In FIG. 6, two voltage divider resistors R6 and R7 are connected in series with each other between an internal supply voltage Vint (for example, a high-level supply voltage Vcc) and a ground (low-voltage supply voltage of 0 V). The two voltage divider resistors R6 and R7 are used to produce a fraction of the internal supply voltage Vint. A constant voltage of an output voltage Vpr is thus developed at an output node that is the junction between the voltage divider resistors R6 and R7. Herein, assume that the internal supply voltage Vint is equal to the supply voltage Vcc and that the voltage divider resistors R6 and R7 have the same resistance. In this case, the output voltage Vpr at the output node is equal to a half of the supply voltage Vcc. The voltage Vcc/2 is therefore developed at the output node. However, a DRAM is required to have reduced power consumption. Power consumption required by the voltage divider resistors R6 and R7 must therefore be as small as possible. Consequently, the resistance of the voltage divider resistors R6 and R7 must be increased to the greatest extent, and the current flowing through the voltage divider resistors R6 and R7 all the time must be suppressed to the greatest extent. However, when the resistance of the voltage divider resistors R6 and R7 is increased too much, the startup characteristics of a supply voltage of the DRAM deteriorates. With regard to the DRAM, it is required to guarantee that the DRAM operates normally after a given time (for example, 200 .mu.sec) has elapsed since the DRAM was powered on (namely, that the DRAM exhibits an excellent startup/response characteristics).
For the constant voltage generating circuit shown in FIG. 6, an effort has been made to improve the startup/response characteristics of the DRAM. Specifically, a first output transistor Q3 realized by an NMOS transistor, and a second output transistor Q4 realized by a PMOS transistor (p-channel MOS transistor) are connected as complementary transistors to the node between the voltage divider resistors R6 and R7. In this case, the first output transistor Q3 and second output transistor Q4 are connected as complementary transistors between the high-voltage power supply and the low-voltage power supply. The sources of the first output transistor Q3 and second output transistor Q4 are connected to a common output node. Thus, a source-follower type power supply circuit is configured.
Furthermore, in the constant voltage generating circuit shown in FIG. 6, the drain of an NMOS transistor Q1 is connected to the gate (node N3) of the first output transistor Q3. The drain of a PMOS transistor Q2 is connected to the gate (node N4) of the second output transistor Q4. Furthermore, the drain of the NMOS transistor Q1 is connected to the high-voltage power supply via a resistor of high-resistance value R4, while the drain of the PMOS transistor Q2 is connected to the low-voltage power supply via a resistor of high-resistance value R5.
Furthermore, in the constant voltage generating circuit shown in FIG. 6, three divider resistors R1, R2, and R3 connected in series with each another are used to produce fractions of the internal supply voltage Vint (for example, the high-level supply voltage Vcc). Thus, two reference voltages of difference levels are produced. More particularly, one reference voltage is developed at a node N1 that is the junction between the divider resistor R1 and divider resistor R2. The reference voltage is applied to the source of the PMOS transistor Q2. On the other hand, the other reference voltage is developed at a node N2 that is the junction between the divider resistor R2 and divider resistor R3. The reference voltage is applied to the source of the NMOS transistor Q1. In this case, the reference voltage developed at the node N1 is set to a level slightly higher than a half of the supply voltage Vcc. The reference voltage developed at the node N2 is set to a level slightly lower than a half of the supply voltage Vcc. These two reference voltages that will be described later in relation to an embodiment shown in FIGS. 10 and 11 are set in order to define a dead zone in which the constant voltage generating circuit is unresponsive to a fluctuation of the voltage Vpr (Vcc/2) developed at the output node. This is intended to prevent the first and second output transistors Q3 and Q4 from becoming operating states simultaneously. When the first and second transistors Q3 and Q4 become operating states simultaneously, a penetrating current flows from the high-voltage power supply to the low-voltage power supply, through the first and second output transistors Q3 and Q4.
Herein, the reference voltage developed at the node N2 is applied to the gate of the first output transistor Q3 through the NMOS transistor Q1. Since the first output transistor Q3 operates as a source follower, the output voltage Vpr that is substantially equal to the voltage Vcc/2 is developed at the output node. On the other hand, the reference voltage developed at the node N1 is applied to the gate of the second output transistor Q4 through the PMOS transistor Q2. Since the first output transistor Q4 operates as a source follower, a voltage that is substantially equal to the voltage Vcc/2 is developed at the output node.
Furthermore, in the constant voltage generating circuit shown in FIG. 6, when the level of the output voltage Vpr at the output node falls below a predetermined value, a voltage between the gate and source of the third output transistor Q3 that is an NMOS transistor becomes an operating state. Consequently, the third output transistor Q3 is turned ON. The high-voltage power supply and output node are then linked by the third output transistor Q3. The voltage at the output node is controlled to rise accordingly, so that the output voltage Vpr at the output node will become substantially equal to Vcc/2. On the other hand, when the level of the output voltage Vpr at the output node becomes higher than Vcc/2 by the predetermined value, a voltage between the gate and source of the fourth output transistor Q4 that is a PMOS transistor rises. The fourth output transistor Q4 is then turned ON. Consequently, the low-voltage power supply and output node are linked by the fourth output transistor Q4. This causes the voltage at the output node to fall. The output voltage Vpr at the output node becomes nearly equal to Vcc/2.
As mentioned above, in the conventional semiconductor integrated circuit including a DRAM, a source follower type power supply circuit is used to produce a voltage corresponding to a half of a supply voltage Vcc. The source follower type power supply circuit as shown in FIG. 6 (first and second output transistors Q3 and Q4) includes MOS transistors that operate as a source follower. However, recently, there has been a tendency toward the request that the DRAM is allowed to operate with a supply voltage which is as low as possible, for example, a supply voltage equal to or less than 2 V. The threshold voltage Vth between a gate and a source of a MOS transistor employed in a source follower type power supply circuit, i.e., the threshold voltage required at the minimum for allowing a current to flow through the source and drain of the MOS transistor is usually about 0.5 V. Reference voltages which are to be input to the first and second output transistors Q3 and Q4 that operate as a source follower are supplied via the NMOS transistor Q1 and PMOS transistor Q2.
Here, assume that a voltage applied between a gate and a source of the first output transistor Q3 is VGS (Q3) and a voltage applied between a gate and a source of the second output transistor is VGS (Q4). Further, assume that a reference voltage at a node N1 is V (N1) and a reference voltage at a node N2 is V (N2). Furthermore, assume that the threshold voltage between a gate and a source of the NMOS transistor Q1 is Vth (Q1) and the threshold voltage between a gate and a source of the PMOS transistor Q2 is Vth (Q2).
In this case, a voltage VGS (Q3) applied between a gate and a source of the first output transistor Q3 corresponds to a voltage which is produced by subtracting the output voltage Vpr (.apprxeq.Vint/2) at the output node, from a value obtained by adding up the reference voltage at the node N2 which is about Vint and the threshold voltage Vth (Q1) between a gate and a source of the NMOS transistor Q1. On the other hand, a voltage VGS (Q4) applied between a gate and a source of the second output transistor Q4 corresponds to a voltage which is produced by subtracting a value obtained by subtracting the threshold voltage Vth (Q2) between a gate and a source of the PMOS transistor Q2 from the reference voltage at the node N1 which is about Vint/2, from the output voltage Vpr (.apprxeq.Vint/2) at the output node. The above relationship can be expressed in the following equations (1) and (2). EQU VGS(Q3)=(V(N2)+Vth(Q1))-Vpr(.apprxeq.Vint/2) (1) EQU VGS(Q4)=Vpr(.apprxeq.Vint/2)-(V(N1)-Vth(Q2)) (2)
Assuming that an internal supply voltage Vint is a supply voltage Vcc and that this supply voltage Vcc becomes 2 V or less than 2 V, the sum of the threshold voltages Vth (Vth=0.5 V+.alpha., where .alpha. is an increment by which Vth is increased due to a back bias, and is about 0.2 V) approaches to the level of a half of the supply voltage Vcc (herein, the output voltage Vpr at the output node=Vcc/2.ltoreq.1.0 V) so that the sum of the threshold voltages is substantially equal to the level of a half of the supply voltage. Therefore, as is obvious from the above equations (1) and (2), the voltage between the gate and source of each of the first output transistor Q3 and the second output transistor Q4 shown in FIG. 6 may therefore not be sufficiently greater than the threshold voltages Vth. The output transistors Q3 and Q4 thus may have difficulty in stably operating as source followers.
The effect brought about the above-mentioned back bias is derived from a variation in threshold voltage Vth of a MOS transistor in accordance with a voltage between the source and the back gate. In particular, the threshold voltage of a MOS transistor operating as a source follower varies depending on an output voltage. The threshold voltage is therefore actually a little higher than 0.5 V as mentioned above.
Consequently, when a supply voltage becomes less than 2 V, the output transistors Q3 and Q4 in the constant voltage generating circuit shown in FIG. 6 cannot fully exert the driving ability necessary for operating as source followers. This causes problems in that the circuit operation for generating a voltage used to precharge bit lines or a voltage which is to be applied to the cell plate node of a cell capacitor in a memory cell cannot be achieved stably.